The capacitor utilized for CPU (central processing units) for personal computers and the like is required to have high capacitance and low ESR (equivalent serial resistance) so as to suppress the fluctuation of voltage and reduce the heat generation at the passing of a high ripple current.
Generally, as a capacitor for use in a CPU circuit, two or more aluminum or tantalum solid electrolytic capacitors are used.
Such a solid electrolytic capacitor is constituted by an aluminum foil having fine pores in the surface layer or a sintered body of a tantalum powder having fine pores in the inside as one part electrode (electric conductor), the dielectric layer formed on the surface of the electrode, and the other electrode (usually, semiconductor layer) provided on the dielectric layer.
The method for forming the semiconductor layer of the capacitor using a semiconductor layer as the other electrode includes, for example, a method of forming the semiconductor layer by means of energization described; for example, in the specification of JP. Nos. 1868722, 1985056, and 2054506. This is a method of forming the semiconductor layer by immersing an electric conductor having provided on the surface thereof a dielectric layer in a semiconductor layer-forming solution, and applying a voltage (passing a current) between the electric conductor serving as a positive electrode and an external electrode (negative electrode) prepared in the semiconductor layer-forming solution.
JP-A-3-22516 (the term “JP-A” as used herein means an “unexamined published Japanese patent application”) describes a method of forming a semiconductor layer by passing a current having a DC bias current superimposed on an AC current to an electric conductor provided with a dielectric layer. Further, JP-A-3-163816 describes a method of bringing an electric conductor into contact with a chemical polymerization layer on a dielectric layer and forming a semiconductor layer on the chemical polymerization layer by electrolytic polymerization using the electric conductor as a positive electrode. Such methods involve problems in a case of forming a semiconductor layer in multiple conductors simultaneously. That is, the method described in JP-A-3-22516 involves a problem that a semiconductor layer is formed also on the negative electrode and the state of forming the semiconductor layer changes by lapse of the current supply time and, further, it is not ensured that the current flow is uniform to in each of the multiple electric conductors. Further, in the method described in JP-A No. 3-163816, since current is supplied by using the electric conductor placed outside as a positive electrode, it is not ensured that a semiconductor layer is uniformly formed in the inside of each of the electric conductors. Particularly, this results in a significant problem for an electric conductor of a large size whose inside pores are minute.